Non-volatile electronic memory devices are widely used in several apparatuses, such as cell phones, digital cameras, notebooks, etc., where storing a considerable amount of information in a compact memory with high capacity is required.
Semiconductor integrated non-volatile memory devices have been developed, which comprise a plurality of memory cells organized in a matrix, i.e., the cells are organized in rows called word lines WL and columns called bit lines BL, as shown in FIG. 1. The memory cells or active areas are realized, as partially shown in FIG. 2, in a semiconductor substrate 1 and are separated from each other by portions of a field oxide layer FOX.
Each cell comprises a floating gate transistor with a floating gate region FG above a channel region CH or tunnel oxide formed in the semiconductor substrate 1. The floating gate regions FG are separated from one another along the word lines, as highlighted in FIG. 4 and in the detail illustration of FIG. 5, by an STI layer and by the layers P1 and P2. The STI layer is made of a layer of ONO (oxide, nitride, oxide, the layer P2 is made of a conductive shield such as polysilicon, and the layer P1 is made of ONO, for example.
A control gate region CG is then capacitively coupled to the floating gate region by an interposition of more dielectric layers overlapped to form a layer of the ONO (oxide/nitride/oxide), as shown in FIG. 3.
Each cell has drain, source and body regions. In a matrix-like organization, via metal electrodes, only the drain of the select transistor is contacted near the last cell of the bit line, i.e., the DSL and the source of the transistor near the first cell of the bit line called SSL. The control gate regions are contacted so as to apply predetermined voltage values to the memory cells.
The charge stored in the floating gate region FG determines the logic state of the cell modifying its threshold voltage. The main feature of the memory cell is that of having two states, one with a low or erased threshold voltage, which corresponds to an erased cell, and one with a high or programmed threshold voltage which corresponds to a written cell. Different conventions can be provided. The voltage is externally applied through the control gate region CG, but the electrode effectively controlling the state of the channel is the floating gate region FG.
The need of storing, in a more reduced space, a greater amount of data has led to the development of devices with multilevel memory cells, wherein different logic states are stored in each cell.
For devices with multilevel memory cells, and in particular with cells of the Flash NAND type, the accurate control of the threshold distributions of the cells becomes fundamental so that they are correctly placed below the erase verify potential, for the erased cells, and between the program verify values and the Vpass programmed values for the written cells. The Vpass voltages are the threshold values relative to the voltages associated with the different logic states stored, and their value depends on the number of bits that can be stored in the same cell.
During the programming of a Flash NAND cell, a lot of attention has been paid to the presence of the effective disturbances which could vary the voltage stored in the cell and cause a variation of the voltages stored in the adjacent cells. This is a phenomenon called “widening of the distributions”.
In non-volatile memory devices the undesired capacitive cell-to-cell couplings are among the main contributors for the “widening of the distributions”. In multilevel devices the “widening of the distributions” is more damaging since the thresholds relative to the different values or logic states are separated within narrow voltage intervals.
In a memory of the Flash NAND type, with a high density, the main parasitic capacitive components are identified, with reference to FIG. 9, with the capacitances along:
1. the direction Y of the bit lines;
2. the direction X of the word lines; and
3. direction XY diagonal couplings.
The three parasitic capacitances identified show different values from each other and, typically in the order indicated, they show decreasing values.
Problems of modification of the voltages in the cells and thus of “widening of the distributions” show up when the cells themselves are programmed. In fact, with particular reference to FIG. 6, during the programming of the cells blackened in the drawing there is a modification of the voltages of the corresponding floating gate regions which allow the formation of parasitic capacitances causing a variation of the voltage of the floating gate regions FG of the cell arranged centrally (not blackened in the drawing WL1-BL(n)).
From some experimental data detected and reported in FIGS. 7 to 10, it has been possible to observe, on a block of a non-volatile memory device comprising nine cells, the structure of the parasitic capacitances and to carry out a measuring thereof.
In the example shown in FIG. 7, considering the central cell as the detecting one and considering that the adjacent cells had been erased by a voltage equal to 13V and programmed with an ISPP process, i.e., with a ΔVstep=0.5V and tstep=20 μs, a total value of the threshold value has resulted, due to all the parasitic capacitances which have been formed, equal to 130 mV which is of course a relevant value.
On the same block of cells, moreover, two different measurements of the parasitic capacitances have been detected further to two different formulations and reported in FIGS. 10 and 11.
For the first detection the block of cells had been erased with an erase verify value of about 13V in a time t=1.5 ms, while for the second detection the erase verify erase value was of about 18V in a time t=1.5 ms. For both the detections a programming sequence of the cells has been followed corresponding to the increasing numbers indicated from 1 to 5 in FIG. 9.
In FIG. 10 the values of the total coupling effect on the cells are reported, measured in threshold voltage, due to the parasitic capacitances. The curve indicated with the letter a represents the progress of the threshold voltage due to the coupling capacitances of the cells which had initial voltage values lower than Vthstart≦−0.7V, which according to the current standards, occur with erase verify values equal to 13V. With the letter b the curve is instead indicated when the cells have initial voltage values lower than Vthstart≦−4V, i.e., with erase verify values equal to 18V.
FIG. 11 shows an enlargement of FIG. 10 and the cells highlighted in the same row have been programmed by ISPP, i.e., with identical values of ΔVstep=0.5V and tstep=2 μs. As can be observed from this enlargement, the threshold voltage is transferred to the central cell and this is due to the totality of the parasitic capacitances and is equal to 130 mV during the first detection according to the curve a, and is equal to 360 mV during the second detection, i.e., curve b.
This confirms how the value of the parasitic capacitances significantly influences the threshold voltages of the single cells, and thus the correctness of the programmable and programmed values.
Several approaches are known to reduce the capacitances of type 2 along the direction X of the word lines in the devices of non-volatile memory cells.
A straightforward and efficient approach, for example, is shown in European Patent Application No. 02425805.5, which discloses filling in the space between two adjacent floating gate regions of cells belonging to the same word lines with a material having a low dielectric constant, as shown in FIG. 12. European Patent Application No. 02425805.5 is assigned to the current assignee of the present invention, and is incorporated herein by reference in its entirety.
A further known approach is shown in U.S. Patent Application No. 2004/0012998 to Chien et al., which discloses reducing the capacitive effects of the floating gate regions along the direction of the word lines due to a particular conformation of the word lines themselves in correspondence with an insulating layer or gate oxide STI, interposed between two adjacent floating gate regions FG. This approach, shown in FIG. 13, provides a trench in correspondence with the insulation layer STI allowing an increase in the lateral insulation between the floating gate regions, and an increase in the volume and the area interposed between the floating gate regions and the word lines.
All these approaches reduce the parasitic capacitances in the direction X. However, they do not teach how to reduce the parasitic capacitances along the axis Y.
The parasitic capacitive coupling which is realized along the axis Y is due to the fact that between the word lines an insulating layer is interposed and that two opposite floating gate regions FG, arranged on two consecutive word lines, realize two plates of one capacitor, as highlighted in FIGS. 14 and 15.
This phenomenon has increased along with the increase in the density of the memory cells on the same device, and thus along with the decrease of the distance between the floating gates of cells placed on opposite word lines.
To limit the couplings in the direction Y techniques can be used by varying the geometric dimensions of the floating gate regions. For example, a technique reduces the height of the floating gate regions which reduces the opposite surface.
These approaches, however, show some drawbacks. In fact, the designation of the dimensions of the floating gate regions influences the programming voltage value and the threshold values which are, especially in the case of a multilevel memory cell device, important values for operation of the device itself. It is thus necessary not to excessively reduce the dimensions of the floating gate regions.
A further known approach to reduce the parasitic capacitances between the floating gate regions uses programming techniques of the non-volatile memory devices with ramp voltages. The main drawback of this approach is that high programming voltages are required.
A further known approach avoids the interposition, between the word lines, of materials with high dielectric constants, such as for example, silicon nitride, or reducing the amount of interposed dielectric.
Generally, as highlighted in FIG. 16, the floating gate regions of non-volatile cell memory devices have lateral spacers partially overhanging the source and drain regions of the present NMOS and PMOS transistors, which are covered by a dielectric layer.
To reduce the amount of dielectric material interposed between the word lines, a known approach increases the length of the spacers, as highlighted in FIG. 17, for example, so that between two opposite floating gate regions arranged on consecutive word lines, there is at least a partial union between the spacers.
This for example, however, shows the drawback that the spacers influence, in a fundamental way, the circuitry of the device. It is thus necessary to take into account the final length of the spacers in relation with the breakdown feature of the present NMOS and PMOS transistors.